The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, more specifically to a semiconductor device characterized by a junction structure between an adhesion improving layer and a capacitor dielectric film used in a storage capacitor formed in a DRAM (Dynamic Random Access Memory) or an FeRAM (Ferroelectric RAM), and a method for fabricating the same.
Recently, as semiconductor devices are more highly integrated and have larger capacities, design rules (line/space) have become increasingly precise. Accordingly, the semiconductor devices, e.g., DRAMs (Dynamic Random Access Memories) have widths of the wiring layers decreased, and the contact plugs connecting the storage nodes which are to be the lower connection electrodes of the storage capacitors to the source regions have smaller diameters.
Such the DRAM comprises cell regions each including one transistor and one storage capacitor, for storing 1-bit information. The storage capacitor comprises a lower electrode called a storage node, an upper electrode called a cell plate, and a capacitor dielectric film sandwiched between the upper and the lower electrodes.
In the conventional DRAM, an electrode material of the storage node and the cell plate is doped polycrystalline silicon, and the capacitor dielectric film is ON film (a composite film of SiO2 and Si3N4) formed by thermally oxidizing the surface of a thin CVD nitride film.
The storage node is formed in a projected electrode structure to use as a capacitor not only the upper surface but also the side surfaces, whereby a sufficient capacitance can be obtained for a limited space (floor area). This has a background that the capacitance cannot be lowered below a prescribed capacitance, e.g., about 30 fF in order to cope with alpha radiation and decrease of the source voltage.
In addition, DRAMs have been developed with the integration improved by about 4 times every three years, i.e., the micronization improved; the projected structure of the storage capacitor, i.e., the projected structure of the storage node tends to become higher and higher so that a sufficient surface area can be ensured for a decreased capacitor floor area.
However, as the storage capacitor structure becomes higher, a height difference from the peripheral circuit region becomes larger. This resultantly causes a problem that the wiring layer becomes thin at the step, and the wiring becomes less reliable, and, in the exposing step, a problem of a depth of focus that the higher region and the lower region cannot be simultaneously focused.
On the other hand, although the above-described problems can be solved by planarizing with an insulation film to be equalized the height with the higher surface, there occur additional problems that contact holes in the peripheral circuit regions become deeper, making the etching difficult and that the contact holes of such high aspect ratio cannot be filled with a metal electrode material of low resistance.
Then, a material having a higher dielectric constant, i.e., a high dielectric constant film is required in place of the conventional ON film (a composite film of SiO2 and Si3N4) as the capacitor dielectric film. Such the high dielectric constant film is used to thereby obtain a higher capacitance per a unit area. Studies of obtaining a required capacitance without increasing a height of the projected structure of the storage capacitor are made. This produces an advantage of simplifying steps of the fabrication.
As such the high dielectric constant film, the use of Ta2O5 film, SBT (SrBi2Ta2O9) film, BST ((Ba,Sr)TiO3) film, etc. are studied. These high dielectric constant materials are basically oxides, and have a problem that when these films are deprived of oxygen, these films become conductive, and leak current tends to flow in the films.
DRAMs store information in charges stored in the storage capacitors. Seriously, increase of leak current means extinction of information stored in the DRAMS.
The storage node and the cell plate of the conventional storage capacitor are formed of polycrystalline silicon. Polycrystalline silicon can be easily deprived of oxygen. In using a high dielectric constant film as the capacitor dielectric film, it is vital to use an electrode material which take place of polycrystalline silicon.
An electrode material suitable for such the high dielectric constant film must satisfy the following (1) to (6) requirements:
(1) Oxygen defect which is a cause for depriving a high dielectric constant film of oxygen to cause leak current does not take place.
(2) An electrode material itself does not diffuse in the high dielectric constant film to cause deterioration of the high dielectric constant film.
(3) An electrode material is able to withstand high-temperature annealing for crystallizing the high dielectric constant film.
(4) The electrode material can be easily etched.
(5) An electrode material has a resistance as low as possible.
(6) An electrode material has good adhesion with a base insulation film, so that peeling does not take place after heat treatment.
However, it is very difficult to satisfy all the six requirements from (1) to (6), and no electrode material which satisfy all of the requirements has been so far found. Electrode materials, for example, Ru (Ruthenium) and RuO (Ruthenium Oxide), can satisfy, to some extent, the requirements (1) to (5) but does not satisfy the requirement (6).
That is, a Ru film and a RuO film have a defect that they tend to peel from the insulation film.
Then, in order to solve such defect of the peeling of these electrode films, which is their only one defect, it is considered to provide below such electrode materials an adhesion improving layer having good adhesion with the base insulation film for the prevention of the pealing of the electrode materials. As such the adhesion improving layer, TiN, WN, and Ta, etc. are prospective.
Here, with reference to FIGS. 38A and 38B, the storage capacitor of the conventional DRAM using Ru as the storage node and having the adhesion improving layer will be explained.
FIG. 38B is a plan view of the DRAM at the time that a lower plug 75 of the DRAM is formed. FIG. 38A is a sectional view of the DRAM. In FIG. 38A, the layer structure up to a first inter-layer insulation film 69 is a sectional view along the one-dot chain line B–B′ in FIG. 38B, the layer structure from a second inter-layer insulation film 72 to a third inter-layer insulation film 74 is a sectional view along the one-dot line A–A′ in FIG. 38B, and the layer structure thereabove is a sectional view again along the one-dot chain line B–B′ in FIG. 38B. In FIG. 38A, the layer structure below the third inter-layer insulation film is represented conveniently by A–A′ to simplify the showing.
In FIG. 38A, for convenience, a bit line 73 is shown, shorted to the lower plug 75, but they are positionally isolated from each other as shown in FIG. 38B.
Reference will be made to FIGS. 38A and 38B.
First, a device isolation oxide film 62 is formed by selective oxidation in a prescribed region of a p-type silicon substrate 61. Then, the exposed surface of the p-type silicon substrate 61 surrounded by the device isolation oxide film 62 is thermally oxidized to form a gate oxide film 63. Next, a non-doped polycrystalline silicon film is deposited, and an impurity, such as P (phosphorus) or others, is ion-implanted. Then, the polycrystalline silicon layer is etched into a prescribed pattern to form gate electrodes 64 and word lines 65, which are extensions of the gate electrodes 64.
Actually, an SiO2 film or an Si3N4 film as a protection film is provided by CVD method on the gate electrodes 64.
Then, as the gate electrodes 64 as a mask, an impurity, such as As (arsenic), P or others, is ion-implanted to form an n+-type drain region 67 and an n+-type source region 68. Then, an SiO2 film is deposited on the entire surface by CVD method and is subjected to anisotropic etching to form sidewalls 66.
Instead, in the above-described ion implanting step, As ions are implanted to form an LDD (Lightly Doped Drain) in a shallow n−-type region, and the sidewalls 66 are formed. Then, P ions are implanted to form the n+-type drain region 67 and the n+-type source region 68.
Then, an SiO2 film is deposited on the entire surface by CVD method to form the first inter-layer insulation film 69. A via hole for the n+-type drain region 67 and the n+-type source region 68 is formed. A TiN (titanium nitride) film to be a barrier metal and next a W (tungsten) film, etc. are deposited by CVD method or sputtering method, and are polished by CMP (Chemical Mechanical Polishing) method to form contact plugs 70, 71 with the W film, etc. buried in.
Next, an SiO2 film is deposited on the entire surface by CVD method to form the second inter-layer insulation film 72, and a via hole for the contact plug 70 is formed. Then, a doped polycrystalline silicon film, a WSi2 film, etc. are deposited on the entire surface by LPCVD (Low Pressure Chemical Vapor Deposition) method and then patterned to form the bit line 73.
Next, again an SiO2 film is deposited on the entire surface by CVD method to form the third inter-layer insulation film 74, and a via hole for the contact plug 71 is formed. Then again a W film is deposited on the entire surface by LPCVD method and polished by CMP method to form the lower plug 75 buried in the via hole.
A TiN film and an Ru film are sequentially deposited on the entire surface by sputtering and then etched to form the adhesion improving layer 76 and a storage node 77 in a projected shape. Then, again a Ta2O5 film and an Ru film are sequentially deposited by sputtering and etched into a prescribed shape to form the capacitor dielectric film 78 and the cell plate 70. Thus, a basic structure of the DRAM is completed.
In this case, the storage capacitor is constituted by the storage node 77, the cell plate 79, and the capacitor dielectric film 78 sandwiched by both, and is electrically connected to the n+-type source region 68 via the adhesion improving layer 76, the lower plug 75, and to the contact plug 71.
However, in the storage capacitor using such the adhesion improving layer 76, the adhesion improving layer 76, and the capacitor dielectric film 78 of the Ta2O5 film contact directly to each other at both ends of the adhesion improving layer 76 circled by the dotted lines. At these ends, oxygen in the Ta2O5 film diffuses in the TiN film forming the adhesion improving layer 76 to cause oxygen defect in the Ta2O5 film. As a result, a problem of deterioration of the capacitor dielectric film 78 is caused.
That is, the adhesion improving layer 76 of TiN film, etc. satisfy the requirements (4) to (6) out of the requirements (1) to (6) but does not satisfy the requirements (1) to (3). Accordingly, there occurs the problem that the high dielectric constant film at the sidewall of the adhesion improving layer 76 is degraded, and leak current undesirably flows.
In order to solve this problem of deterioration of the high dielectric constant film on the sidewall of the adhesion improving layer 76, it is considered to from the adhesion improving layer 76 in a buried structure. Such improved storage capacitor will be explained with reference to FIGS. 39A and 39B.
FIG. 39A shows a sectional view of the same part as FIG. 38A. FIG. 39A, however, omits, the structure on the side of p-type silicon substrate 61, and another transistor commonly using an n+-type drain region 67 so as to simplify the explanation.
In FIG. 39A, the view on the right side is a view showing the positional relationship between a storage node 77 and the adhesion improving layer 76.
Reference is made to FIG. 39A.
The structure up to the third inter-layer insulation film 74 is formed in completely the same way as in FIG. 38A. Then, a via hole arriving at the contact plug 71 is formed and then filled with the lower plug 76 of W film by CMP. Then, the lower plug 75 is over-etched to form a cavity in the via hole. Then, a TiN film is deposited and polished by CMP method to be buried as the adhesion improving layer 76 in the cavity.
Hereafter, an Ru is deposited in the same way as in FIG. 38A and is etched into a prescribed shape to form the storage node 77 in a projected shape. Next, again, a Ta2 O5 film and an Ru film are sequentially deposited by sputtering method and etched into a prescribed shape to form a capacitor dielectric film 78 and a cell plate 79. Thus, a basic structure of the DRAM is completed.
In the case that the adhesion improving layer 76 is thus buried, the Ta2O5 film forming the capacitor dielectric film 78 is kept out of direct contact with the adhesion improving layer 76, whereby deterioration of the capacitor dielectric film 78 never takes place.
However, as the integration of the DRAM is improved, an alignment allowance between the storage node 77 and the adhesion improving layer 76 is so small that, in view of the alignment precision of the current exposure systems, it is actually impossible to prevent, without failure, the adhesion improving layer 78, accordingly the lower plug 75, from appearing beyond the storage node 77. This causes additional problems. These problems will be explained with reference to FIG. 39B.
FIG. 39B is a sectional view of the same part as FIG. 39A.
Reference is made to FIG. 39B.
As shown by the view on the right side in FIG. 39B, in the case that the lower plug 75, accordingly the adhesion improving layer 76, appears beyond the storage node 77, the adhesion improving layer 76 and the capacitor dielectric film 78 contact directly to each other in the part circled by the broken line in the view on the left side in FIG. 39B. At this part, the deterioration of the capacitor dielectric film 78 takes place, causing leak current.
In addition to an area of the adhesion improving layer decreased by the buried structure, when such disalignment takes place, an area of the contact between the adhesion improving layer 76 and the storage node 77 becomes smaller, which causes an additional problem of the peeling of the storage node 77.